طراحی فیزیکی غیرقابل قبول مبتنی بر اینورتر بسیار سبک وزن و قابل تنظیم Ultra-lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

I. INTRODUCTION NOWADAYS non-volatile memory (NVM) based security mechanisms are widely used in conventional security systems, in which binary encrypted keys are stored and authenticated to access stored secret information. However, with the development of attacking techniques, e.g. side channel analysis (SCA), the keys stored in NVM are vulnerable to adversaries [1]. To address this issue, PUF designs have been investigated by researchers to improve hardware security [2] [3]. A PUF is a security primitive that utilises unpredictable fabrication variations to encrypt integrated circuits (ICs) to provide unique identifying information. The random variations in chips that are produced under the same fabrication process can lead to different unique responses when presented with the same input challenge. When an input (challenge) is sent to a PUF circuit, a unique output (response) will be generated. PUFs can use these CRPs to authenticate devices and distinguish genuine devices from fake ones. Hence, PUFs can be applied to key generation [4] [5], radio-frequency identification (RFID) security [6] [7] and IP protection [8] [9]. Commonly, PUFs are categorised into delay-based PUFs and memory-based PUFs [10]. Delaybased PUFs focus on extracting the differences in the propa gation delay of signals and memory-based PUFs detect the instability in memory cells when powered up. To date, a number of delay-based PUF designs have been proposed to exploit the various types of fabrication variations in IC, e.g. Arbiter PUF [11] [12] and RO PUF [13]. Memory-based PUF designs have been proposed including static RAM (SRAM) PUF [14] [15], Butterfly PUF [8], FPGA ID generator [16], etc.. RO PUF is one of the most promising designs due to its reconfigurability, high uniqueness and reliability. RO PUF is composed of RO pairs based on the basic RO unit [2]. To generate a single bit response of a conventional RO PUF design, two symmetrical and route-balanced ROs are used to produce two different frequencies and one 1-bit response is decided by comparing two frequencies. A counter and a comparator are used to generate one bit output, either ‘0’ or ‘1’. This architecture incurs large power and area overheads. Configurable RO PUFs have been proposed to improve the reliability and hardware resource usage of RO PUF [13] [17] [18] [19], where multiplexers (MUXs) are used to select one of two inverters and thus the number of CRPs increased and the hardware consumption is decreased.