Xilinx SDNet 2018.2

The Xilinx SDNet™ Development Environment for networking, in conjunction with Xilinx FPGA and SoC devices, allows for the creation of next-generation hardware-accelerated software-defined networks. SDNet supports packet processing functionality with high throughput and low latency. It allows for game-changing differentiation through software-programmable data plane hardware with content intelligence that dynamically collaborates with control plane software. This addresses the performance, flexibility, and security challenges of modern content-oriented, intent-based, and zero-touch, networking.

Software-Defined Programmability
SDNet enables the development of software-defined data plane hardware, featuring support for the modern P4 packet processing language. It adds some novel generalizations to current P4 that permit effective harnessing of the unique white box hardware capabilities of Xilinx devices. These allow the system architect to define exact fit hardware for particular network requirements, in contrast to potentially wasteful fixed-resource ASIC alternatives. SDNet also creates standard runtime software APIs into the P4-programmed data plane, ensuring that investments in standard software stacks for slow-path packet processing and network operation and management, are protected.

The unique capabilities unleashed by SDNet with its P4 programming model enable carriers and MSOs to dynamically provision unique, differentiated services without any interruption to the existing service or the need for hardware re-qualification or truck roll. This enables service providers to reach higher revenue potential with unprecedented CapEx, OpEx, and time to market savings. Network equipment providers and network-attached server providers realize similar benefits from the feature-rich, flexible hardware platform that allows for extensive differentiation through the deployment of content-aware data plane hardware.

Particular benefits enabled by SDNet include:
- Improved, highly flexible quality of service
- Flow-and-session-aware capabilities
- Fully programmable hardware data plane and input/output
- Support for network functions at wire speed including user-defined, custom capabilities
- Scalable line rates from 1G to 400G
- Packet classification for security applications such as intrusion prevention and detection (IPS/IDS) and deep packet inspection (DPI)
- Packet generation and checking for L2-L7 protocol testers
- Custom protocol processing in defense and military applications

This implementation flow allows system architects to focus only on the services they are looking to provision without having to focus on exactly how those services are being implemented.