Electronics system design techniques for safety critical applications
- نوع فایل : کتاب
- زبان : انگلیسی
- مؤلف : Luca Sterpone
- ناشر : Berlin : Springer
- چاپ و سال / کشور: 2008
- شابک / ISBN : 9781402089794
Description
Contributing Author........................................................................................xi Preface ..........................................................................................................xiii Chapter 1: An Introduction to FPGA Devices in Radiation Environments ................................................................................. 3 From the architecture to the model 1. Previously Developed Hardening Techniques ............................... 6 1.1 Reconfigurable-Based Techniques........................................... 7 1.2 Redundancy-Based Techniques ............................................... 8 Chapter 2: Radiation Effects on SRAM-Based FPGAS ............................... 17 Modeling and simulation of radiations effects 1. Radiation Effects .......................................................................... 18 1.1 Single Event Upset (SEU)...................................................... 19 1.2 Single Event Latch-Up (SEL) ................................................ 20 2. SEU Effects on FPGA’s Configuration Memory......................... 21 3. Simulation-Based Analysis of SEUs............................................ 23 3.1 Simulation Environment ........................................................ 23 3.2 Fault Simulation Tool............................................................. 26 3.3 Experimental Results.............................................................. 28 4. Hardware-Based Analysis of SEUs.............................................. 30 4.1 Details on the Xilinx Triple Modular Redundancy................ 32 4.2 Analysis of TMR Architecture............................................... 32 4.3 Experimental Results.............................................................. 35 5. Robustness of the TMR Architecture........................................... 37 5.1 Analysis of the Fault Effects .................................................. 39 6. Constraints for Achieving Fault Tolerance .................................. 42 2. Preliminaries of SRAM-Based FPGAS Architecture .................. 11 2.1 Generic SRAM-Based FPGA Model..................................... 11 2.2 FPGA Routing Graph............................................................. 13 Chapter 3: Analytical Algorithms for Faulty Effects Analysis..................... 47 Single and multiple upsets errors 1. Overview on Static Analysis Algorithm ...................................... 49 2. Analytical Dependable Rules ....................................................... 51 3. The Star Algorithm for SEU Analysis ......................................... 52 3.1 The Dynamic Evaluation Platform......................................... 54 Dependable design on SRAM-based FPGAs 1. RoRA Placement Algorithm ........................................................ 73 2. RoRA Routing Algorithm ............................................................ 76 3. Experimental Analysis.................................................................. 79 Chapter 5: A Novel Design Flow for Fault Tolerance SRAM-Based FPGA Systems...................................................... 85 Integrated synthesis design flow and performance optimization 1. The Design Flow .......................................................................... 87 1.1 STAR Analyzer ...................................................................... 88 1.2 RoRA Router.......................................................................... 89 2. Performance Optimization of Fault Tolerant Circuits ................. 89 2.1 The Congestion Graph ........................................................... 90 2.2 The Voter Architectures and Arithmetic Modules................. 91 2.3 The V-Place Algorithm .......................................................... 92 3. Experimental Results.................................................................... 93 3.1 Timing Analysis ..................................................................... 94 3.2 Evaluating the Proposed Design Flow ................................... 96 3.3 Evaluating a Realistic Circuit................................................. 97 Chapter 6: Configuration System Based on Internal FPGA Decompression........................................................................... 103 A new configuration architecture 1. Introduction to the Decompression Systems.............................. 103 2. Overview on the Previously Developed Decompression Systems ............................................................ 105 2.1 Generalities of SRAM-Based FPGAs.................................. 107 Chapter 4: Reliability-Oriented Place and Route Algorithm ........................ 71 4.2 Experimental Results of MCU Static Analysis...................... 67 4.1 Analysis of Errors Produced by MCUs.................................. 58 4. The Star Algorithm for MCU Analysis........................................ 56 3.2 Experimental Results of SEU Static Analysis ....................... 55 Chapter 7: Reconfigurable Devices for the Analysis of DNA Microarray.................................................................................. 117 A complete gene expression profiling platform 1. Introduction to the DNA Microarray ......................................... 117 2. Overview on the Previously Developed Analysis Techniques .................................................................. 119 3. Preliminaries of DNA Microarray Image Analysis ................... 121 3.1 The Edge Detection Algorithm ............................................ 122 4. The Proposed DNA Microarray Analysis Architecture............. 123 4.1 The Edge Detection Architecture......................................... 125 4.2 The Quality Assessment Core.............................................. 128 5. Experimental Results.................................................................. 129 Chapter 8: Reconfigurable Compute Fabric Architectures ......................... 133 A new design paradigm 1. Introduction to RCF Devices...................................................... 134 2. The ReCoM Architecture ........................................................... 135 3. The Proposed System ................................................................. 108 4. Experimental Results.................................................................. 111 4.1 Compression System Results ............................................... 112 3. Experimental Results.................................................................. 141 Index............................................................................................................ 143