Intel Quartus Prime Standard Edition 18.1.0.625

The new revolutionary Altera Quartus® Prime Pro design software includes everything you need to design for Altera® FPGAs, SoCs, and CPLDs from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements, are providing designers with the ideal platform to meet next-generation design opportunities. For designers to effectively take advantage of these devices, software must dramatically increase design productivity. The new Quartus Prime software, built on the successful Quartus II software, is breaking barriers of FPGA design productivity with an additional Spectra-Q™ engine that is optimized for Arria® 10 and future devices.

Altera’s Quartus® Prime software provides everything you need to design with Altera® PLDs, including FPGAs, SoCs, and CPLDs. It is a complete development package that comes with a user-friendly GUI and best-in-class technology to help you bring your ideas into reality. Learn more about the new and exciting features available in the Quartus Prime software.

Qsys Pro
Qsys Pro is the next-generation system integration tool in Quartus Prime Pro Edition software, and builds on the capabilities of Qsys, which is supported in Quartus Prime Standard Edition software. Both Qsys and Qsys Pro save significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.

Synthesis
The Spectra-Q™ Synthesis Tool is the new synthesis engine, which integrates a new front-end language parser into the Quartus Prime software. With the new front-end parser, designers will see improved language support for all IEEE register transfer level (RTL) languages. This includes expansive support for SystemVerilog-2005 and VHDL-2008. Support for all previously supported languages is also maintained.

BluePrint Platform Designer
The BluePrint Platform Designer leverages the new Spectra-Q engine to explore a device’s peripheral architecture and efficiently assign interfaces. BluePrint prevents illegal pin assignments by performing fitter and legal checks in real time eliminating complex error messages and the need to wait for a full compile, speeding up your I/O design by 10X.

Physical Synthesis
Quartus Prime software includes physical synthesis optimization technology. Quartus Prime physical synthesis options are applied during the fitting stage of the compilation process and can be applied regardless of the synthesis tool used.

Hybrid Placer
The Spectra-Q engine also includes a new Hybrid Placer feature that uses advanced placement algorithms to speed up overall logic placement. The Hybrid Placer combines analytical and advanced annealing techniques for overall improved quality of results and a reduction in seed noise enabling faster timing closure.

PowerPlay Power Anaylzer
Altera’s PowerPlay power analysis technology features Excel-based PowerPlay early power estimators (EPE) and the PowerPlay power analyzer tool in the Quartus Prime software. These power analysis tools give you the ability to estimate power consumption from early design concept through design implementation.

DSE
The Quartus Prime software includes the next-generation Design Space Explorer (DSE), an easy-to-use design optimization tool, with an updated flow-oriented user interface, guiding users through the tool. DSE automates the process of finding the optimal collection of Quartus Prime software settings for a design to help you achieve timing closure, optimize area, and reduce power consumption. This updated tool also allows users to customize the Quality of Fit metric, which can be used to judge which exploration points are better.

TimeQuest Timing Analyzer
TimeQuest timing analyzer is the second generation, easy-to-use timing analyzer which leverages industry-standard Synopsys® Design Constraints (SDC) support to achieve accurate timing, resulting in faster timing closure.

System Console
System Console is a system-level debug tool that helps you to quickly and efficiently debug your FPGA design in real time using read-and-write transactions.

SignalTap II Logic Analyzer
The SignalTap™ II Logic Analyzer provides a system-level debugging tool that captures and displays real-time signal behavior.

At the heart of Altera’s Quartus® Prime design software is the new Spectra-Q™ engine, which enables new levels of design productivity for next-generation programmable devices. The Spectra-Q engine consists of faster, more scalable algorithms, a new hierarchical database infrastructure, and a new unified compiler technology. The Spectra-Q engine enables the development of new tools and design flows and further extends Altera’s Quartus Prime software leadership by delivering:
- 8X faster compile times using improved algorithms, incremental optimizations, and distributed compilation
- 10X faster I/O design by creating legal pinouts at design start
- 5X faster design entry by raising the level of design abstraction