طرح مدار لچ متحمل به SEU بر اساس DICE عایق شده و المنت های کم مصرف A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Abstract Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed IsoDICE latch consumes 50% less power with only 45% of power delay product in TSMC 90 nm CMOS technology. Under 22 nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance. ۱٫ Introduction With the progress of semiconductor process, digital circuits are becoming more susceptible to noise due to reduced working supply voltage and increased transistor density. In the advanced VLSI environment, the circuits are more easily affected by alpha particles, cosmic rays, and heat particles to cause errors, which are all summarized as soft errors [3–۸]. The advancement in nanoscale CMOS technology allows increase in circuit density and improvement in performance while reducing cost. However, the enhancements in reducing transistor size and supply voltage cause decrease in the parasitic capacitance of the circuit internal node which results in the reduction of the critical charge (critical charge is the minimum charge required for maintaining the correct logic state). Consequently, the reliability of circuits against soft errors lowers and low-energy alpha particles or cosmic rays can easily cause interference in circuit internal nodes, which results in instantaneous voltage transient error [3–۸]. Soft errors can be categorized into two classes according to the different locations of occurrence: (1) single event transients (SETs) which occur in combinational circuits, and (2) single event upsets (SEUs) which occur in storage elements, latches, or register nodes when the logic state of circuits changes undesirably. Due to the WOV (Windows of Vulnerability) of sequential circuits is longer than combinational circuits, sequential circuits are usually more susceptible to particle strikes than combinational circuits [9], [10]. As illustrated in Fig. 1, the SEU dominates around 90% of soft-error occurrence in modern VLSI circuits [10]. Moreover, the WOV of latch circuits is much longer than that in the flip-flop circuits. Therefore, most recent researches focus on devising robust schemes for latches. In this paper, we will further present a robust latch design that not only performs with superior soft-error resistant capability but also with lower power delay product (PDP). In the existing literature designs, a variety of methods have been used to increase the SEU tolerance capability of latch circuits, such as: (1) interlock circuits with a redundant feedback path, such as Dual Interlocked Storage Cell (DICE) [1]; (2) strengthening equivalent capacitance for those internal nodes which have low critical charge, such as Schmitt Trigger latch (ST) [11]; (3) increasing the number of nodes to have the same electrical potential, such as SEU-A design [12]; (4) latches capable of filtering and masking SEUs, such as feedback redundant SEU-tolerant latch (FERST) [2]; and (5) constructing redundancy circuits together with a voting circuit to determine the valid output, such as Triple-Modular Redundancy (TMR) [13–۱۵]. Among these SEU-tolerant approaches, DICE design can provide good SEU tolerance with less hardware cost and FERST design can provide even superior SEU-tolerance. TMR can also provide superior and nearly perfect SEU-tolerance; however, it is always criticized for its hardware complexity since it requires three times the circuit area. Therefore, in this paper we proposed a new SEUtolerant latch that can provide superior SEU-tolerance as FERST latch but with much lower PDP. Our proposed design is based on DICE architecture because of its advantages of simplicity. To further enhance the SEU-tolerance of DICE latch, we proposed an isolating technique which is capable of masking soft-error between DICE circuit’s internal and output nodes. The proposed Iso-DICE latch can have both the DICE latch’s capability of masking SEUs by cross-coupled inter-latching and the FERST latch circuit’s isolation concept of having more than two storage points. Therefore, the Iso-DICE latch can have a higher SEU tolerance with a smaller power-delay-product while efficiently preventing output nodes from being affected by the SEU in the internal nodes of latch circuit. In order to evaluate the SEU tolerant capability of each latch, some simulation experiments are carried out by means of HSPICE with TSMC 90 nm CMOS technology model, 65 nm, 45 nm, 32 nm, and 22 nm predictive technology model [33]. To confirm the consistency of comparison results, we use a variety of benchmark circuits and simulate them for particle attacks with different striking energy for performance evaluation. The remaining concept of the paper is organized as follows. Section 2 briefly introduces the previous designs. Section 3 presents the proposed SEU-tolerant latch, describes its circuit operation, and its SEU-isolation mechanism. Section 4 demonstrates the performance comparison results. Finally, a conclusion is made in Section 5.