تاثیر و توجیه کاهش دیواره درین القا شده بر روی MOSFET 100 نانومتری با دی الکتریک های گیت K The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

۱٫ Introduction As MOSFET size continues to scale down to sub100 nm, the thickness of SiO2 is reduced to keep a sufficient current driving capability. However, when the thickness of SiO2 is thinner than 1.5 nm, the direct tunneling current increases dramatically, which becomes a main limiting factor in complementary metal oxide semiconductor (CMOS) technology.[1] High-k materials as alternative dielectrics are widely studied, and have larger physical thicknesses to prevent direct tunneling.[2] Unfortunately, a side effect called fringing-induced barrier lowering (FIBL) becomes a serious threat to reliability when the thickness of the gate dielectric is comparable to the channel length.[3] With the increase in the physical thickness of the gate dielectric, the electric field lines originating from the bottom of the gate electrode and terminating on the source and drain region increase.[4] These electric lines form an electrical field originating at the drain, penetrating into the channel through the high-k dielectric and suppressing the barrier height from the source to the channel.[5] This causes lower threshold voltage, worse sub-threshold swing and increased off-state current.[6] In this paper, the off-state current is used to characterize the degradation of devices with high-k gate dielectrics. Some research has been conducted to understand the effect of FIBL on the device and circuit performances of MOSFETs with high-k gate dielectrics.[7−۱۰] FIBL is investigated using different device structures, such as the effective oxide thickness, the gate length, the junction depth, and the spacer width. However, these studies have not explained the physical mechanism of the FIBL effect thoroughly. Mohaoatra et al. [11] proposed an equivalent electrical distance theory to describe the FIBL effect, but the influence of the spacer on the device characteristics has not been included. In the present paper, an equivalent capacitance theory is proposed to explain the physics mechanism of MOSFETs with high-k gate dielectrics. For the first time, the equivalent capacitance is used to describe the influence of the FIBL effect. By analysing the factors affecting the capacitance, the physics behind the FIBL effect can be explained. The influence of structure parameters on FIBL is investigated using the two-dimensional device simulator ISE–TCAD. The effect of the gate dielectric stack on device performance is also presented. ۵٫ Conclusion A comprehensive analysis of FIBL in sub-100 nm MOSFETs with high-k gate dielectrics is investigated using two-dimensional numerical simulations. An equivalent coupling capacitance theory is proposed, which gives better insight into the physics of the FIBL phenomenon. The coupling effect of the drain electrode on the channel through different kinds of paths enhances the FIBL effect and induces a large off-state current, which can be controlled by combining a lowk spacer, short spacer width, low junction depth and small gate/LDD overlap length. The stack gate dielectric is shown to suppress the FIBL effect, in particular when the permittivity of the bottom layer is smaller than that of the top layer.