طراحی CPU بر اساس زمان بندی سخت افزاری و ثبات های خط لوله مستقل CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

THE use of the current commercial and free real-time operating systems (RTOSs) for embedded systems encounters, in our opinion, two major problems. While the first one refers to the interrupt handler, the second addresses the fact that a task cannot synchronize simultaneously with events used for synchronization, resource sharing, and communication. Such events would be signals, semaphores, mutexes, messages, flags, and others. These problems were identified in RTOSs that run on microcontrollers without a virtual memory management unit and cache memory. Examples include the following RTOSs: μITRON, μTKernel, μC/OS-II, EmbOS, FreeRTOS, SharcOS, XMK OS, eCOS, Erika, Hartik, KeilOS, and PortOS. The first problem, generated especially by the interrupt service routines on the simultaneous occurrence of many interrupts, is the jitter. Because of it, it is difficult to calculate the worst case execution time, an important component of the real-time systems. This can lead to deadline misses. A second problem is the extension of the task’s execution time. This extension is generated by successive calls of the RTOS application programming interface (API) functions used to detect the occurrence of one of the events listed above. Another important issue is the time spent by RTOSs for task context switching (context switching is an operation carried out by the RTOS scheduler that requires a lot of time). Furthermore, API function calls become time consuming, especially if the processor requires transition from the user mode to the supervisor mode, and vice-versa. The current general-purpose processors are used for embedded systems, but they can create problems, mainly due to nondeterministic performance and inefficient power consumption. In order to avoid these problems, conservative design techniques may be adopted. These techniques can create an oversized platform, enabling the proper behavior under worst case conditions. As a consequence, the use of these processors has limited applicability and they are unsuitable for the embedded systems with hard real-time features and low power consumption requirements. On the other hand, currently, field-programmable gate array (FPGA) devices [1], [2] at more efficient prices and with equivalent capacity in logic gates (more than millions) are widespread [3], [4]. For this reason, we propose a hardware support for real-time OS functionalities [5], based on the FPGA systems. We present a custom scheduler architecture that is a hardware design with replication of resources [program counter (PC), pipeline registers, and CPU general purpose registers] as defined in [6] and [7]. Our architecture is based on the microprocessor without interlocked pipeline stages (MIPS) architecture that was especially adapted to support the operation of the hardware scheduler as part of the CPU itself. It employs a set of four pipeline registers for each task, used to hold the running instructions of the CPU. The register file is replicated for each task. This allows a very fast context switching, simply by remapping the active context of the task to be executed. This architecture, called multipipeline register architecture (MPRA) in [7], replaces the stack saving methods with a remapping algorithm that enables the execution of the new task starting with the next clock cycle. The new architecture is characterized as follows: it contains an original implementation of the hardware structure used for static and dynamic scheduling of the tasks, it enables unitary management of the events and interrupts, it provides access to shared resources, event generation, and also defines a method used to attach interrupts to tasks, thus ensuring an efficient operation in the context of real-time requirements. The aim of the new architecture is to improve for microcontrollers the performances of the RTOSs. The performances are related to the following: task switching time, response time to external events, behavior of the interrupts, and execution time of the synchronization interprocess communication (IPC) primitives (events, mutexes, messages, and so on). This paper is organized as follows. The nMPRA architecture is presented in Section II, and the nHSE architecture, including all RTOS facilities implemented in hardware, is presented in Section III. Section IV presents a series of tests carried out during the implementation of the proposed architecture. Section V includes related work and the comparisons with the nMPRA architecture. Finally, conclusions are drawn in Section VI.