مبدل DC-DC خازنی کم موج تمام دیجیتال با کنترلر ردیابی بار An all-digital low ripples capacitive DC-DC converter with load tracking controller

1. Introduction Switched Capacitor (SC) DC-DC converters have received high attention over switching based DC-DC converters [1–3]. This is because SC converters use the integrated high-density capacitors with low series resistance in standard CMOS process providing high power efficiency, cost effective, and thus, being a fully integrated solution. However, there are technical challenges in the design of fully integrated SC converters. One of the most important challenges is to support a load current (Iload) with wide dynamic range (e.g. load currents up to 100 mA) while keeping the output voltage ripples (Vripples) lower than 20 mV pp [4,5]. Many techniques have been introduced to lower the level of Vripples such as phase interleaving, Capacitance Modulation (CpM), and time modulation [4,6]. In Ref. [6], a VCO combined with a phase interleaving technique was used to lower the values of the load regulation and Vripples through changing the switching frequency (fsw). This approach showed Vripples close to 50 mV pp for load currents up to 160 mA using 18-phase interleaving. The main limitation of this approach is the need for a VCO with wide frequency range to support a wide dynamic range of Iload. As an example to cover a load range from 0 to 160 mA, Le et al. showed that the VCO frequency has to change from 1 to 300 MHz [6]. Moreover, this approach is a mixed signal solution which is not an all-digital scalable solution. In Ref. [4], the load regulation has been reduced through Pulse Frequency Modulation (PFM). In addition, capacitance and time modulation techniques have been used to further reduce Vripples. This approach results in Vripples that scales with Iload, and thus, this approach reduces Vripples at light loads only. As an example, Kudva et al. shows Vripples of 27 mV pp for load current of 2 mA using a load capacitor of 5 nF [4]. Achieving Vripples lower than 20 mV for load currents up to 100 mA with integrated capacitors in an all-digital solution is still a challenging problem. Combining two or more of the already existing ripple reduction techniques may result in further reduction of Vripples for a load with wide dynamic range. Such an approach requires an optimum controller to achieve the targeted reduction. This controller should guarantee that controls of the power switches are leading to the maximum efficiency and smaller load regulation values while reducing Vripples. Moreover, most of mobile devices are powered by batteries with nominal supply voltage of 3.6 V while digital circuits need a supply of ∼1 V. Such a high voltage difference between input and output voltage would stress the transistors of any advanced technology node, e.g. 0.13 μm and less. One possible solution is to use cascaded thin-oxide transistors and use level-shifters to avoid the breakdown⧵stress of the devices [6].